On: A Case for Self-Managing DRAM Chips

[buescher]

But you have that handshake anyway now, between the CPU and the memory controller, effectively at least, don't you?

[wmf → buescher]

No, you don't. AFAIK DRAM chips just sit idle until the memory controller gives them a command and then they perform the command immediately.

[buescher → wmf]

But the memory controller still has to refresh them. So at some point you have to negotiate a wait state, don't you?

[londons_explore → buescher]

Yes - everything 'upstrram' of the memory controller has variable latency, partly because of the chance that a read or write request has to wait for a refreshing operation.

[mistrial9 → buescher]

they design for a very, very small edge on the signal state transition.. so yes technically but its meant to be negligible, I believe.. (not a hardware designer but I have looked over the shoulder a few times)

[mumumu → wmf]

They can sleep, but waking up has a large latency.