DRAM have self refresh mode.
Provides no evidence that putting more logic into the DRAM will somehow be cheaper
With that being said, it gets a bit nuanced, because as we make faster and faster DRAMs, we need more complicated input/output electronics (Phy and ECC.) GDDR actually has self refresh as part of the spec and even allows DRAM vendors to put a PLL inside so you can run a half rate clock, which technically makes it "Quadruple Data Rate" instead of "Double Data Rate." But usually with GDDR, you're running one controller per DRAM. Clamshell mode is not super common in my experience.
 I'm not super well versed on DDR4 and all of its configurations. So someone who is can elaborate if they would like.
Both of those things would be possible while implementing the regular 'dumb' dram interface, but any error detection or remapping would have to operate within the latency budget of the module, since the latency is fixed. Typically that means not much remapping can be done, and ram yields have to be really good.
With this change, ram becomes robust to far more silicon defects like nand flash is. That's what makes it cheaper.