I've a possibly silly question: since cache misses can dominate performance even in the single-core case, why don't they use all that silicon to make one core with craptons of on-die cache?
Presumably because at a given level of performance L2 cache size and die size/complexity don't have favorable scaling properties. You can ask this question to Google almost verbatim and find articles talking about SRAM ports and stuff.
The beauty of multicore scaling is that it scales.
