Agner on microarchitecture [1], page 213, another mention as a bottleneck on page 216:
The Ryzen supports the AVX2 instruction set. 256-bit AVX and AVX2 instructions are split
into two µops that do 128 bits each.
AVX2 increased register width from 128-bit (AVX) to 256-bit, yet Ryzen cores can only process them 128-bit at a time. There is more to AVX2 than just width but that means in comparison to Intel processors, which can do the full 256-bit in a µop, the Ryzen throughput will suffer in tests that heavily emphasize AVX2 instructions (think video encoding).
