I'm not really sure the point of your post. Why should I roll my own relational query engine in Scheme when I can use one with hundreds of man-years of development, and thousands of man-years of testing behind it, like PostgreSQL?
Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc.
I am an EE. I have designed fully-synthesized ASICs in Verilog for money. If you ignore the simulation constructs of Verilog (which you should, if you're designing something to be synthesizable), Verilog is a purely declarative reactive language, and a damn good one at that. (Verilog, BTW, has stratified programming-in-the-large constructs.)
You can't synthesize "functional programs"; there's no analogue of recursion in hardware. You can only synthesize things that happen to look like functional programs because they're written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is.
I guess it would be more accurate to say, when I was trying to learn Verilog, people I knew tried to convince me to abandon Verilog in favor of Haskell flavors. This gave me the (perhaps false) impression that this was common practice.
It's not common but many swear by it in form of Bluespec: a Haskell extension/modification for HDL with RTL output. Look them up. Further, dig in the CHERI project for their processor source as it's Bluespec for a security-enhanced, MIPS64 processor which might give you a good idea about what the language is like. Very real-world project. Already runs capability-secure FreeBSD. Most newcomers' Verilog projects are less complicated. :)
Also you might find Synflow's HDL interesting. It's on my backlog as I'd rather get diverse and experienced HDL users to put it through the paces. They have several, non-trivial IP for sale that they coded in it and for cheap, too.
Note: DDD scheme also supported call/cc. :P It wasn't in the final circuit, though, except as an execution feature.
"You can only synthesize things that happen to look like functional programs because they're written using sexprs and macros and expand out to a static circuit graph which is exactly what Verilog is."
Oh, come on, that's kind of cheating as you could say the same about almost any level of abstraction. You might as well say you can't synthesize the Verilog constructs: you just synthesize something that looks like it into a connection of analog transistors that it actually is. Yet, if you can use that model and it works, then it's a meaningful thing to say you can synthesize/use such a model to get X done with Y benefits instead of hand-stitching cell libraries and gates. Likewise, the more functional (or other) alternatives to Verilog with their advantages so long as they deliver on them in the field.
For my examples, SHard is a research prototype that works on some, limited examples. DDD was used on numerous real-world projects while the spin-off was still in business. Gone now. Bluespec is still kicking ass in industry. So, Bluespec at the least proves out the concept and its advantages over Verilog.
They have a great hardware synthesis tool now that costs low, five digits. Just for math-style algorithms rather than arbitrary programs. Prototype algorithm is Matlab language, then deploy to HDL with plugin.
Also, I sincerely hope you're not trying to synthesize ASICs out of code from a language with constructs like call/cc.