This presentation did not include the P&L slide he showed recently in London[1] (excellent presentation at Monkigras). They took huge cashflow risks and were very lucky to survive.
Yes, we were definitely lucky, although the cash flow risk wasn't on purpose! Some things happened in that graph that were out of our control. The lesson from that graph is don't count your money until is in the bank and don't sell a product until it's on the shelves.
With only $6M raised, this whole venture is probably a 100 to 1 moonshot to be honest with you.(although as an entrepreneur clearly I have to believe the odds are better than that...). Calxeda raised $100M and went bust, Tilera raised $150M and was sold for $50M, Tabular raised $200M and went bust, the Cell processor supposedly cost $1B to develop, etc.
If you are interested, here is a long list of parallel processor efforts. All of them failed to reached general purpose status:
From your history slides, I thought of Mill OoBC http://millcomputing.com/docs/; they share the DSP roots, do you know them or their work ? they don't design many-core cpus though.
ps: Also, I don't think there was mention of your previous work on the Kickstarter page or boards, was it on purpose (NDA,...) ? Past projects like these really give trust to future clients.
The reality is that there are not many business uses for massively parallel computation in a small package. This affects large FPGAs as well. The only real market is in the defense industry where price is no object but it is also a very risk averse industry and is unlikely to take a chance on a startup that could go under at any time not to mention that it prefers parts fabbed on special lines from approved vendors. Software shops aren't going to take a risk on leaving the world they know and are more likely to bang their head trying to make conventional DSPs work if a normal processor won't cut it.
"The reality is that there are not many business uses for massively parallel computation in a small package."
Yet. People will want good voice recognition. Even if you cannot get that in your phone, your provider will want an energy-efficient solution for running voice recognition for millions of users simultaneously.
Further ahead is the babelfish.
Your phone also may want to use its cameras to figure out who is talking, and adjust its noise suppression depending on the location of the speaker.
Finally, car manufacturers will want small, low-power, cheap stuff to build their self-driving cars.
Hardware like this may strike the right balance between flexibility and power use for problems such as these.
And yes, this may be too weird for most to take the risk of using it, but it may take only one succesvol company to make the jump.
Well here is a counter-point: don't ignore the marketing / coolness factor of new technology. It may not be entirely rational from a risk/cost perspective, but given that software engineers are interested in new technology, you could get a sale. Also there is value for marketing your product if it's based on new technology.
(Otherwise I generally agree with slides: software and features are much more important than performance).
One thing which is rational and helps FPGAs is time to market (vs. a giant SoC with long verification time). If you can get your design to market sooner than anyone else you get to charge a premium which could pay for the extra per-chip cost of FPGAs vs. ASICs.
Interesting chip, but not even an SoC so I'm curious what the market will be.
It would be interesting to have a tile-based chip like this, but with an FPGA-style I/O ring (I mean support many common interfaces including serdes-based but also allow the interchip links). Perhaps you end up with a new form of FPGA.
The way the presentation keeps mentioning IP makes me think that the chips are just a demo and they want to license the IP to be embedded in someone's SoC.
The truth is that big market companies rarely if ever buy from chip startups. With new technology, the best forward is to partner with a larger company and license the IP. (see cognivue, mobile eye as great example in the automotive market). Still, we will continue to sell our chips and boards to anyone who wants them for as long as we are around.:-)
28nm is pretty cutting edge (many, many steps) and has a number of customers (competing for manufacturing line time).
It's a bummer, but it's a long process. Not to mention, each new chip you spin is $$$, so it's not like you would iteratively fab many prototypes, even if you had a fast turnaround time.
I've heard that a fab run itself is 6 weeks, so maybe 3 months including packaging sounds reasonable. 28nm Bitcoin ASICs have been done in that time frame.
OTOH, if you can't get the fab time below 11 months maybe you should spend more like 24 months on the design.
If you co-design the package, then a realistic test shuttle fab turn around time is ~4 months. It also depends on how early you were in the process. Doing shuttles in 28nm in 2011 was definitely bleeding edge. Clearly something happened to push out the sample delivery to 11 months..
[1] https://twitter.com/justincormack/status/561128891348422657