PLLs are fascinating. Software PLLs are less fun than messing with the hardware, in my experience!
I started working on a software PLL recently -- not analog like this one, digital. Specifically, I was trying to work out the math on a fully event driven type-II PLL -- i.e. instead of updating at a fixed sampling rate, it'd wake only when an edge happened on the input or VCO. I was starting to get curious whether there's a solution for that somewhere on the web.
Warning: You need ~three semesters of EE under your belt to grok the math used in this blog post. Incidentally at that point you dont need that blog post because this stuff is trivial and self explanatory. This makes me very confused. It almost reads like a solution to an assignment you would get in DSP class.
Man, EE is what I do for fun, and DSP is what I write every day. I can't even follow this without sitting down and spending hours on it, so don't feel bad.
For anyone interested, here's the essence of a phase-locked loop:
Say you're climbing up a long staircase and the step height increases suddenly - then you'll bump into the next step. If the height were to go the other way i.e; decrease, then you'll put your foot down hard trying to place the next step. That change in step height is in fact a change in frequency, and you're forced to adjust your pace abruptly by adjusting the timing (phase) of your subsequent steps.
Is there a 'gentler' way to adjust the phase? Now say you're wearing some kind of spongy sandals that can take up the slack, so at every step you increasingly sense that the frequency has changed. This accumulation indicates that phase is mathematically the integral of instantaneous frequency with respect to time.
We now put this integral in a feedback loop. Then, if the staircase step height changes suddenly we use the slow accumulated phase to produce an error signal that gradually drives the frequency generator (in this case, our brain) to adjust the pace of our step till we get in lock-step.
The actual dynamics is more complicated, involving a non-linear frequency capture (which linearizes the system) and then the slower phase lock. You can see this in the waveforms in the original post.
Lot of great things happening in SDR, especially since the RTL-SDR devices opened the field to more exploration, even in spite of their limitations. Examples like this are exposing more and more people to DSP as well, and that gives me hope for the future of learning.
I started working on a software PLL recently -- not analog like this one, digital. Specifically, I was trying to work out the math on a fully event driven type-II PLL -- i.e. instead of updating at a fixed sampling rate, it'd wake only when an edge happened on the input or VCO. I was starting to get curious whether there's a solution for that somewhere on the web.
This is a good intro to (hardware) PLLs in general: https://www.youtube.com/watch?v=0jzLDe950AY followed by http://www.ece.tamu.edu/~spalermo/ecen620.html