Sorry if this is detailed somewhere on the site... but does it run from the mainline Linux kernel? Or do you need additional patches and/or binary blobs?
I was hoping you would go with a MIPS64 architecture rather than the MIPS32 as 'leap' over the current bunch. Also no SATA? Network storage is ok but local SATA for an SSD would be nice.
Fair enough, the Pi killer is a dual core 64 bit SoC with a GB ethernet port, a SATA port, a 1080p/60 capable GPU, and support for 2 - 8GB of DDR4 memory. That is like the 21st century set top box thingy, and possibly throw around computer. At a MSRP of < $50 (which makes it killer) (PSU, case, ssd, monitor etc all extra of course).
It's still 32 bit, only has 1GB RAM and it's $91 at Digikey, but the Olinuxino A20, from Olimex seems to meet just about all of your other criteria.
I've only used the A10, which is $42, but single core, no flash, no analog audio jacks, and for some maddening/expensive reason, 0.05" headers, instead of the 0.1" on the A20.
It's a little behind the bleeding edge of Linux (still at 3.4), but I've been able to port an app from a beaglebone black to this with virtually no headaches. In fact, it's been nice, since there is no device tree at 3.4. Best of all, it's readily available, unlike the BBB.
Open source graphics? Intel (they actually have an open source driver team), then AMD (they at least provide decent hardware documentation), then pretty much everyone else ships binary blobs and doesn't document anything.
Big parts of the VideoCore IV (Raspberry Pi) are documented - though not completely (especially the video acceleration unit is not yet publicly documented, officially for the reason that you have to pay license fees for some video codecs):
Why the choice to go with a locked down GPU? Apart from openness concerns what about people who don't want to use Linux? Folks who write their own OS or use it bare-metal? This is a real downside to the RPi right now.
I've been wanting to do stuff with MIPS instead of ARM, but this board won't be it.
It's a pretty standard RISC about halfway between SH4 and ARM in RISCiness(TM).
It's memory map is a little different. (For MIPS32 at least, not sure what KSEG of MIPS64 looks like) 80000000-9FFFFFFF is fixed to a cached view of the first 512MB of physical memory. A0000000-BFFFFFFF is fixed to an uncached view. Everything else is only accessible by mapping it via the MMU (both from a physical and virtual context). Last I played with MIPS cores, they were only soft fill TLBs, but maybe that's changed. Thumb2 is more expressive than MIPS16 IMO (but that's just, like, my opinion, man).
Other than that, the microarchitectual differences between individual implementations greatly outweigh the influence of the ISA, but for an in order design at least you can probably make a MIPS that'll compete well with an ARM for less transistors.
