To be technical, Moore's law is about the number of transistors on an integrated circuit.
So your point isn't too far off the 3D comments elsewhere.
Simply making the die bigger doesn't get you much: larger dies (without additional redundancy) have lower yields (as you're more likely to have a defect given a constant defect/area rate) and fewer can be stamped out of a standard sized wafer.
However, if you carry that idea to its logical conclusion... we may turn from shrinking the transistor to shrinking the packaging as the path of least resistance. 3D transistors, chip stacking (aka PoP), and through-silicon vias (aka vertical connectivity) all help get us more processing / area (while remaining within fundamental thermal, manufacturing, etc. physical limits).
Again, this is a CS major with an architecture interest, so anyone please feel free to correct me if I'm off-base.
Silicon photonics is likely to be a huge source of potential improvements. A former Intel SVP, Pat Gelsinger, was quoted as saying "Today, optics is a niche technology. Tomorrow, it's the mainstream of every chip that we build."
http://en.wikipedia.org/wiki/Silicon_photonics
3D doesn't help very much. We're already at the limits of thermal capacity for consumer-chips. 3D just exacerbates that, since now you've lost a whole dimension you can shunt heat through.
If you go 3D, you need a very large drop in heat dissipation to keep your junction temperatures down.
To be technical, Moore's law is about the number of transistors on an integrated circuit.
So your point isn't too far off the 3D comments elsewhere.
Simply making the die bigger doesn't get you much: larger dies (without additional redundancy) have lower yields (as you're more likely to have a defect given a constant defect/area rate) and fewer can be stamped out of a standard sized wafer.
However, if you carry that idea to its logical conclusion... we may turn from shrinking the transistor to shrinking the packaging as the path of least resistance. 3D transistors, chip stacking (aka PoP), and through-silicon vias (aka vertical connectivity) all help get us more processing / area (while remaining within fundamental thermal, manufacturing, etc. physical limits).
Again, this is a CS major with an architecture interest, so anyone please feel free to correct me if I'm off-base.