I'm guessing the study from 2007 is a bit stale now. Intel/AMD/... have almost certainly been trying to decrease the penalty for context switches. I'm curious how much they've changed over time.
I'm not an OS guy, but most aspects of context switching is implemented in software. It seems to me the only places in hardware that could help, would be faster memory access (which is more of a general optimization!) and the TLB. Awkwardly though, x86 doesn't seem to have a TLB insert command, so you just have to miss...?
Oh, and you could shorten the pipeline to make flushes faster and the penalty smaller. But pipeline length has stayed fairly static.
It's interesting that x86 only seems to have TLB tagging for VM guest/host switching usage. Regular context switches require TLB flushing, which (reading the Linux kernel) either flush the entire TLB or a specific set of entries.
I'm surprised no (more) tagging is used here for regular switches. Just not worth it?
Edit: A colleague pointed me to this: http://www.google.com/patents/US6510508 which is used by recent AMD cpus. Anyone know any resource that has more info like this centralized?
Most x86 CPUs from 386 and forward have hardware support for context switching. Generally a hardware solution is superiour to a software solution speedwise, but they're not complete and therefor mainstream operating systems are not using them.
My understanding is the old P4 architecture had an exceptionally long pipeline (75 instructions?); would those have been the primary desktop CPU in 2007?
