EDIT: And if you want to read/write the same memory areas from multiple cores, it's your own responsibility to either get the timing right, or use other means (e.g. you can trigger interrupts in another core) to signal when it is safe for another core to access data.
EDIT: And if you want to read/write the same memory areas from multiple cores, it's your own responsibility to either get the timing right, or use other means (e.g. you can trigger interrupts in another core) to signal when it is safe for another core to access data.