I believe the problem here are the Xilinx tools. They basically suck. Latest Quartus from Altera can build a decent sized (about 10000 LUTs) design in about 10 minutes in my I5 M2520 notebook.
I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!
I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable.
In both tools most of my design spins take <3 minutes.
If you were building an ASIC you'd pay $$$,$$$ for such tools. The economics of FPGAs are such that the tools are either free or $,$$$. Both are reasonable and accessible to an enthusiast/practicing EE, respectively.
I am so grateful to Ross Freeman, inventor of FPGAs, and all the engineers that followed in his footsteps, for democratizing access to state of the art high performance digital logic. For $100 or so you can get a 28 nm device filled with 10,000s of LUTs and hundreds of RAM blocks and build whatever you can imagine. Amazing.
I'm currently synthesizing a 45nm ARM cortex-M0 design using Cadence Encounter flow. The complete process (RTL compiler+place+route) takes only 5 minutes!