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  entity and_entity is
    port( 
      x, y: in std_logic;
      result: out std_logic
    );
  end and_entity;
 

It took a couple of minutes of staring to realize that it was a way of representing the concept of just splicing 2 wires into a 3rd.

To me, it's making an always-on connection, such that any electricity on either line "x" or "y" will induce an identical electrical current on "result". This would obviously include any electrical signals, including HIGH/LOW pulses. And they're combined, so HIGH on either "x" or "y" outputs HIGH on "result".

Because of how I read code, I see that as: whatever is in buckets "x" and "y" are combined and copied into bucket "result".

I've never thought of lines, buses, leads, wires, etc as buckets. Yet that's how I think they're described in this code. But if you think about an individual clock cycle frozen in time, some wires have HIGH pulses, and the intention is to copy the HIGH pulse from that wire/bucket.




That code fragment is really just the pin-out of a block - or to a software person, it's basically a functional interface. Naming aside, it could be the pinout of a number of number things - it could an and gate like this, or one of the signals could be a clock and this is a register... or an entire delay line.

A really interesting mental-model barrier to watch hardware newbs overcome is to present them with designing a counter - and watching as the very first thing they want to type is a for loop, which is generally not how you'd do it, but almost reflexive to someone who has been programming for a while - particularly in an imperative style.

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