The article is quite short on details but I wonder if this is an ARM core that can also execute IBM Z, or the other way around; in other words, which ISA does it execute its first instruction at the reset vector? In that past I've worked on a conceptual design for an "x86+" CPU, which would start as a regular x86 but then be able to execute code of other architectures like ARM, MIPS, PPC, etc. isolated in their own code segments, similar to how V86 mode works.
IBM's mainframes do not really have a reset vector, the CPU gets initialized by some external means into whatever state the OS expects and then the clock gets enabled, so that distinction is quite moot.
