It's a whole bunch of hard IP containing both cores, and you only get a bunch of AXI interfaces into/out of the FPGA fabric. Nothing in the system interconnect looks to be configurable.
My clueless guess is, it's something with the L2-310 cache controller.
Not in this device, cf. https://docs.altera.com/r/docs/683126/21.2/cyclone-v-hard-pr...
It's a whole bunch of hard IP containing both cores, and you only get a bunch of AXI interfaces into/out of the FPGA fabric. Nothing in the system interconnect looks to be configurable.
My clueless guess is, it's something with the L2-310 cache controller.