On: Your Very First Microprocessor

[tcas]

Didn't expect to see Verilog on the front page of HN.

1 nit pick, I think wherever you use a wire assignment you need the assign keyword. e.g

  wire [1:0] command = mem_out[7:6];
  wire [2:0] destination_addr = mem_out[6:3];
  wire [2:0] source_addr = mem_out[2:0];

should be

  assign wire [1:0] command = mem_out[7:6];
  assign wire [2:0] destination_addr = mem_out[6:3];
  assign wire [2:0] source_addr = mem_out[2:0];

Or maybe it's wire assign. I usually first declare the wire in a single statement then use assign on a new line.

[PieSquared → tcas]

Could this be dependent on the Verilog version? At the very least, the wire assignments without the 'assign' keyword seem to work in the iverilog simulator as well as Altera's Quartus suite synthesis tools. I have seen both conventions (wire declaration and assignment separately or together), but I believe the assign keyword is only required for the former.

[PieSquared → PieSquared]

For future reference (since I can't edit): I spent a while researching and couldn't find any definitive answer, but found some places which supported the implicit assignment ([0], [1]). However, these aren't anything official, so I think ultimately it just depends on what your particular implementation supports...

[0] http://www.verilogtutorial.info/chapter_2.htm [1] http://www.doulos.com/knowhow/verilog_designers_guide/wire_a...

[tcas → PieSquared]

You're right. I just tested it in Xilinx ISE 13.4 and it seemed to work without using any assign as both a single wire and a bus. I just recall seeing an error message at some point in the past which was about something similar.

[jgw → PieSquared]

I took a quick look at the IEEE 1800-2009 LRM (SystemVerilog, a proper superset of Verilog), and I can't see any BNF production that allows this. I think this is a case of iverilog being somewhat permissive.

In looking it up, I did come across the keyword "alias", which I was not familiar with, that effectively does what you've done here.

That said, it doesn't detract from an enjoyable tutorial. It's nice to see a little ASIC content on HN - duly upvoted!

[PieSquared → jgw]

Thanks! Nice to know. I must've picked the habit up before from just reading code on the internet (as per my other comment in this thread), but I'll try to phase this out. This is what I love about Hacker News - people commenting really know their stuff, almost always well enough to teach me something :)

[jgw → PieSquared]

Well, apparently I don't know what I'm talking about at all - it does work in the 3 major simulators. Typo in my code. Ooops.

It appears to be valid, and does not require "assign".

This is what I like about HN - smart people keeping me on my toes!

[coffee_bender → tcas]

Assigning the wire on the same line it is declared is supported in all major synthesis and simulation tools I have used. I'm not sure what verilog standard its from, but I would guess its part of verilog 2001.