On: RISC-V Is Inevitable: State of the Union Keynote Argues

[brucehoult]

> Why can't anyone build a performant RISC-V cpu?

"They" can, and are. Many "they"s.

> I'm starting to get the feeling that there is something fundamentally broken in the RISC-V specification that fundamentally limits performance.

Then you are at loggerheads with many legendary ISA and chip designers.