If it were possible, it would have been done already. The issue is the capacitors are already tiny, and barely can prevent a single bit decaying before refresh.
do you have a reference to exact / realistic scaling laws for the leakage currents as function of capacitor/dielectric dimensions and access transistor dimensions?
using 4 (or 2^N) voltage levels stores 2 (or N) bits, so we can afford to make the structures larger
why would this approach make sense for NAND flash but not DRAM?
