On: Libre-Chip Awarded NLnet Grant to Prototype a CPU Isn't Vulnerable to Spectre

[westurner]

openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup

There are various optional feature flags for RISC-V.

The RISC-V open ISA is probably advantageous especially for research implementations.