I think the metastability can't destroy a chip thing is not true, you can get a flop into a state where it's oscillating at whatever freq the internal feedback path is (maybe up to GHz) rather than resolving to a stable 1 or 0. That can propagate to adjacent flops resulting in a bunch of flops pulling too much current.
Like anything to do with metastability this is a statistical thing - it can do this, but it's highly unlikely.
I worked on a chip in the mid 90s where we were very careful about our clock crossings, dropped in special high-gain anti-metastability flops, designed logic to reduce synchronised signal frequencies etc etc all the good stuff - we calculated that we'd see a failure (and mostly that would be a pixel burble on the screen) every year or so - at the time Win95 couldn't stay up a week so management decided to ship it
In the late 90's, I administered the software test lab including UNIX workstations and Windows beige boxes I had build in addition to some servers, the LAN, and WAN for a nuclear engineering consultancy. There were a few Windows 95/98 boxes that were imaged for testing and contained 4 handy-dandy clones that could be copied (prior to widespread usage of Ghost). It would regularly stay running for a month at a time when disused, but I believed it was set to simply reboot to the first primary partition on BSOD. I bet at least one of event logs probably contained entries like these because centralized syslog/log shipping and monitoring weren't set up.
CS/EE here. Malfunction still leads to dragons overall. The problems of sequential logic looping to itself and talking to the outside world under various conditions include (but aren't limited to): getting predictable initialization, predictable durability, matching input impedance, and creating chips with characterizable and reliable setup/hold/delay/etc. times.
These days, I leave chip design to chip designers and barely do silly things like create seven (7) total 4 pin to 3 pin Arduino PWM fan controllers with MOSFETs, MOSFET protection and noise reduction circuitry. See, I have to keep the fans fed with over 4 volts so the tach signal continues and the storage array's BMC doesn't freak out. (The fans characteristics I needed aren't/weren't available in 4 pin PWM.) I try not shock myself like ElectroBOOM or release too much magic smoke from gear or vintage gear that might not be replaceable.
Like anything to do with metastability this is a statistical thing - it can do this, but it's highly unlikely.
I worked on a chip in the mid 90s where we were very careful about our clock crossings, dropped in special high-gain anti-metastability flops, designed logic to reduce synchronised signal frequencies etc etc all the good stuff - we calculated that we'd see a failure (and mostly that would be a pixel burble on the screen) every year or so - at the time Win95 couldn't stay up a week so management decided to ship it