On: Open-Source RISC-V: Energy Efficiency of Superscalar, Out-of-Order Execution

[eigenform]

I'm not sure this sentence [from the paper] makes a lot of sense. The only thing non-standard is the use of Chisel (and then probably CIRCT to lower it into Verilog) - if you're actually taping these out, you're still feeding that to industry-standard EDA tools.