Generally the x um or y nm of a process refers to transistor dimensions (typically gate length), not metal. Minimum metal pitch is still a key dimension for the ability to build useful structures though, so advances like these are very useful.
No, the gate length on most 5nm nodes is like 40nm or something. Since around 2008-ish, the “process name” and the size of any feature have rapidly diverged (even if you use some weird pointless metric like the size of a FinFET fin, nothing on 5nm measures 5nm).
Ironically, prior to 2008 the process name was backwards the other way, for example 130nm process usually has something like 70nm gates.
It’s always really just been a marketing thing anyway, since the possible density of a given logic unit in a given manufacturers process will differ due to a huge number of factors.
Just to reiterate: in old-skool HS electricity terms, a transistor is going to need enough electrons. That number is pretty large, and is tied pretty strongly to materials and geometry. Those two things (materials & geometry) change far slower than Moore's law. What changes quickly is gate density and design cleverness.
There's no tie to what those terms mean and the actual engineering of the chips.
The "2nm node" is a marketing term to indicate its placement relative to previous iterations and competitors.
The reality is that process nodes are complicated and capturing it with a single number would be a bad idea. You could go for raw transistor density which would be better but it misses a lot of the nuances in design.
