> This paper continued TSMC’s trend over the last several years of presenting marketing papers at IEDM instead of technical papers. [...] there are no pitches in the paper, no SRAM cell size, and that graphs are all relative
Sigh. So basically we assume this is all aspirational spin and that either they haven't finalized the parameters for the process yet or they know the numbers will be disappointing already.
The era of VLSI scaling is over for sure. Hilarious that Intel's complete failure at process development happened at exactly the moment where it could do the least damage.
That's not what they're saying - they say it's been a trend over the past several years. VLSI scaling is still continuing, and the article mentions that TSMC seems to have the best numbers, though at higher per-die cost than the authors expected or found reasonable.
Right, that's the spin. You have to put a "seems to" on "have the best numbers" because there are no numbers. If there numbers were the "best", then they would give them. They did not. So... they probably aren't. Or there are other complexities they don't want to reveal.
> If there numbers were the "best", then they would give them. They did not. So... they probably aren't.
I'm not sure that we can say that. They may be keeping their cards close to their chest for any number of reasons. Unless they think they also had "bad" numbers in the past several years when they were doing the same thing.
TSMC publishes industrial research, not pure science research like a university.
In this context the amount of detail they release is careful balance of PR benefit vs. competitive advantage vs. patent status vs. keeping their talent happy because good researches want their names in prestigious journals.
Please. "What is the fin pitch of the process you're releasing next quarter?" is hardly an IP-compromising secret. This stuff is and always has been routine disclosure in advance of technology revisions, analogous to "Our Next Software Version Will Support X and Y". You can excuse it if you insist, but it's pretty clear that we're being primed for 2nm to be at most an incremental improvement.
Sigh. So basically we assume this is all aspirational spin and that either they haven't finalized the parameters for the process yet or they know the numbers will be disappointing already.
The era of VLSI scaling is over for sure. Hilarious that Intel's complete failure at process development happened at exactly the moment where it could do the least damage.