You can work at the polygon level if you really want to, you can write gates and have it lay them out for you (or place them yourself), or work in a higher level language like verilog and have it compile them into gates for you (what most people do) - your choice
How good are things like verilog at producing efficient layouts?
Coming from the perspective of software. Hand coded asm can usually squeeze a lot more than a compiler into a small number of bytes, but that's mostly due to compilers targeting speed of execution instead of size.
Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route.
Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in semiconductor design actually lives. Both of these steps will be affected by the process target. Are you building for an FPGA or CPLD? Which one? If for an ASIC what is the process node? What logic elements are available in your node? Just like when you order a PCB, the process design rules generally come with prescribed information about the manufacturing constraints -- what works and what doesn't. And ultimately you cant rely on hand layout to throw down millions/billions of circuit elements anyway so you have to build solvers and all kinds of other mind bogglingly sophisticated automation to the party.
The diminishing returns of manual optimization here should be evident; if you want to do that work, become a process design engineer.
We do need more open information in this space! Tiny Tapeout is such a great project!
That's all very analogous to software compilers, but doesn't really answer the question I had.
Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there.
Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get closer to a hand crafted approach than that, but I might be wrong.
(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc)
I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons.
Yes you can get better performance and density by laying polygons, especially stuff like ROMs and RAMs and regular ALU structures, but it's a lot of work and not a rathole you want to go down as a beginner
Mostly I'm just trying to explain just how (relatively) hard things are, so people wont get too far out of their depth. I'd really recommend doing the usual HLL/assembler approach - start with a verilog only implementation, build a test bench (tiny tapeout has infrastructure for this), look at the bits you want to be faster/denser, try a hand compiled gates implementation (you can do this within verilog for a start), then maybe even hand lay it out
Yes, I live south of you in Dunedin, though I worked in the SF Bay Area for a couple of decades doing all sorts of stuff including chips, OS's, embedded crypto stuff etc
If you want to do low level design, you can look at the Micro Magic public domain tool set. As someone said above, Verilog only describes the logical function (ranging from the RTL level to the gate level.) You'd need other tools to work on everything physical, like placement and routing.
