Very cool to see that you've achieved a hardware prototype. Looks great.
If you're more interested in exploring your ideas about ternary dataflow computing, is there a reason you didn't start with an FPGA instead? The gap between idea and prototype is much smaller and there's even dataflow DSLs like Tapa if you don't want to write the HDL:
If you're more interested in exploring your ideas about ternary dataflow computing, is there a reason you didn't start with an FPGA instead? The gap between idea and prototype is much smaller and there's even dataflow DSLs like Tapa if you don't want to write the HDL:
https://github.com/rapidstream-org/rapidstream-tapa