Interesting. To give some context to the current problem: the classical (CMOS) logic gates energy is expended to charge or discharge the load capacitance of each electrical node during a state change. Charging a capacitor to a certain voltage requires E=CV^2 amount of (Joules) energy (C in Farads, V in volts). From this, half of it is the energy stored at the capacitor, other half is the energy converted to heat on the transistors. This is so far the most efficient way we can build large scale integrated logic, and at best it is 50% efficient. In reality there is also unwanted inefficiencies, making it close to 30% or so. Good to keep in mind: 100% of the energy becomes heat because the charged capacitor needs to be discharged at some point to change its state. This is becoming a huge thermal management nightmare.
