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Intel’s hyperthreading is really a write pipe hack.

It’s not so much cache misses as allowing the core to run something else while the write completes.

This is why some code scales poorly and other code achieves near linear speed ups.




Why would the core have to wait for the write to complete?

A core stalls on a write only if the store buffer is full. As hyper threads share the write buffer, SMT makes store stalls more likely, not less ( but still unlikely to be the bottleneck).




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