> Or am I totally wrong and the chips are always at the limit of the contemporary technology?
I can chime in here. There are many things that determine the feature size.
There is the process limit, yes, and if your needs are simple digital logic, that's often going to be the density limit.
But if you need NOR flash, there's a stability limit around 40nm process node. You can use smaller transistors for everything else, but soon the NOR is most of the chip.
But what if you need a 1 Amp FET in your PMIC? Well, that won't shrink with process node at all, so maybe a cheaper process node is better to use.
Yes, I was referring to 70's and 80's. Even today, I think, there are applications where 150 nm process is perfectly fine - RFID, transportation cards etc.
If you look at the 74 TTL series dies, they look almost primitive. But perhaps these were one of the first attempts at ICs, so it is expected.
When did transition from hand-drawn to computer-generated designs happen?
You use lots of very small FETs in parallel (and derate the living bejesus out of the SOA curves, because there's no chance that they'll all run at the same temperature.)
Huh? Almost all modern power FETs have positive tempcos. The resulting hotspots (actually hot transistors) are the reason for the SOA curves, and the reason why most modern power FETs don't do well in linear applications.
I can chime in here. There are many things that determine the feature size.
There is the process limit, yes, and if your needs are simple digital logic, that's often going to be the density limit.
But if you need NOR flash, there's a stability limit around 40nm process node. You can use smaller transistors for everything else, but soon the NOR is most of the chip.
But what if you need a 1 Amp FET in your PMIC? Well, that won't shrink with process node at all, so maybe a cheaper process node is better to use.
It really depends.