Amusingly, America's lithography also got nowhere. As you said, ASML now dominates.
Fairchild, Intel, and Global Foundries all stopped producing their own lithography machines.
In that sense Japan has actually exceeded the US in terms of lithography. Of course Chip Design is what keeps the US dominant in the chip war.
> Chip Design is what keeps the US dominant in the chip war.
This is not a solid advantage. Huawei has already proven a few years ago that they can design better chips than Qualcomm, which is when they have been immediately hit with sanctions, preventing them to manufacture their designs at TSMC.
So chip design is a solved problem for them. Replacing the chip design software tools from Synopsys, Cadence and the like is slightly more difficult, but it is still much easier than it seems. The incumbent position of those companies is maintained mostly because only they have access under NDA to the necessary information about the rules of the chip manufacturing processes used by the major foundries. There are no competitors for them mostly because of the absence of public information, not because those programs are particularly difficult to write.
If SMIC or any other Chinese company succeeds to have a competitive CMOS manufacturing process, there will be no difficulty for the likes of Huawei to develop appropriate chip design software tools for those processes.
The only real difficulties are in the physical chip manufacturing, especially in the EUV lithography. However the sanctions will force China to allocate more people and more money than anyone else for solving these problems. There is no doubt that eventually they will succeed. What is unknown is whether they will need 5 years or 15 years.
I think you are a little optimistic that the full EDA flow would be "not... particularly difficult to write." On the implementation side alone, you'd need to write a SystemVerilog compiler, logic synthesis, timing analysis, timing optimization, power analysis, clock gating, coarse placement, global routing, detailed routing, placement legalization, physical design planning, clock tree synthesis, design rule checking, lots more underlying technology to make it work, and lots of steps I'm not remembering. Every one of those sub-areas is it's own specialty. Then you can start thinking about verification.
