That's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins:
So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby!
The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).
Interesting. Saw this on the Wishbone Z80 project notes:
"Guy Hutchison (see TV80 project) has synthesized an early version of the core in a 130nm TSMC process. He determined the design to contain about 20k gates and run at about 240 Mhz. While the speed is somewhat less than "target", optimizations of the logic should increase this somewhat."
Guy Hutchison's TV80 is also mentioned on this project's page.
https://github.com/rejunity/z80-open-silicon/blob/main/docs/...