SiFive Premier P550 RISC-V development board

[fork-bomber]

https://www.sifive.com/boards/hifive-premier-p550

[bee_rider]

I have no idea if this chip is any good, but

> RISC-V is inevitable, and the HiFive Premier P550 development system exemplifies that.

> RISC-V has no limits.

Have to appreciate the chutzpah if nothing else.

[downvotetruth → bee_rider]

> RISC-V is inevitable

have yet to see a normal motherboard where the CPU is socketed (iGPU is a waste of sand on desktop); the ram is slotted and not a soldered upsell - mobile is the market for LPDDR.

[RetroTechie → downvotetruth]

This looks like a SoM + carrier board. So at least in theory one could swap out the SoM (but yes, cpu + RAM soldered on there).

[brucehoult → downvotetruth]

You don't see socketed CPUs and RAM in the Arm SBC world either. Or, increasingly, in the PC world e.g. Apple.

[bee_rider → downvotetruth]

Works for Apple, haha.

[snvzz → bee_rider]

RISC-V is inevitable, RISC-V enables the best processors, RISC-V has no limits.

Are all phrases from the foundation's marketing committee playbook. They encourage using these.

I follows these recommendations. Some find it annoying, but the whole point is ingraining them in everybody's brains.

RISC-V is inevitable.

[rwmj]

It's a shame this isn't P650, which has the Hypervisor extension amongst other things (https://www.sifive.com/cores/performance-p650-670).

[snvzz → rwmj]

Look into Milk-V Oasis, that has 16x P670 + 8x X280, V extension and overall interesting specs.

[rwmj → snvzz]

Looking forward to it, when it arrives, and hopefully it's more stable than the Pioneer.

[snvzz → rwmj]

VisionFive 2 has been solid to me, and it's faster than the Pioneer.

(based on a newer revision of the same U74 core from SiFive)

[brucehoult → snvzz]

I'm not sure in what world a 1.5 GHz four core machine is faster than a 64 core 2.0 GHz machine with not only 1 MB L2 cache per four cores, but 4 MB L3 cache per four cores, all 64 MB of which is usable by a single (or a few cores) when running code without many threads.

The Pioneer uses the C910 core (64 of them, as noted), not U74.

Perhaps you were thinking of the old early 2021 HiFive Unmatched?

[snvzz → brucehoult]

>Perhaps you were thinking of the old early 2021 HiFive Unmatched?

Yup, I was.

[ansible → rwmj]

I would have liked to see at least 8 cores for a development board like this.

[brucehoult → ansible]

It's going to be significantly faster than the 4 core boards we have now. Of course the upcoming 8 core (Banana Pi) and 16 core P670 machines will be better again, later in the year.

[snvzz]

Remarkably. the chip isn't an Intel+SiFive chip as it was meant to be.

I wonder what happened.

[rwmj → snvzz]

Intel killed that board ("Horsecreek") although I don't have any inside information about why.

[Paianni]

eMMC makes this a hard pass for me.

[snvzz → Paianni]

Please elaborate and help us understand your view.

How does having an eMMC onboard make the board useless to you, even if you don't use this feature?

[brucehoult → snvzz]

eMMC is certainly better than an SD card in several ways. And, as you say, you can always ignore it.

Similar, really, to how XTHeadVector is better than no SIMD/Vector, is 95% the same opcodes and functionality as RVV 1.0, is now well-supported in GCC 14, and you can always ignore it, no?

[Paianni → snvzz]

If the eMMC failed then the board would become a brick until the associated chips were desoldered and replaced.