Tinytapeout 6 closes in a couple of weeks https://tinytapeout.com not too late to knock out your own chip.
The basic idea is that you buy a chunk of a die, your design's pins get multiplexed to the outside, you pay a bit extra and get a dev board
Chips take time - I taped out my 2 TinyTapeout CPU designs over a year ago, the board arrived a couple of months ago, TT3 is (as I understand) almost in the mail (I have a PDP8 there), and TT4 silicon has just come back (I have a RISCV subset there), TT5 is at the fab, and TT6 tapes out in 2 weeks.
Real silicon works like this, you start on a (big) design, do the creative stuff for a couple of months, for a year you test it to hell, by the time you tapeout you're done with it, then you start on the next design, about the time you're in the middle if doing the fun creative bit the old silicon comes back
Does anyone know how much memory is available on board to each design for the tiny tapeout project? If each project could include something like a FPGA Block RAM I feel the project would have (much greater) utility and flexibility. Although I understand that might not be possible.
You have to make your own, some people have SRAM compilers - depending on how big a tile you choose the more memory you get (it's going to be in the 100s to low 1000s of bits)
The course sounds brilliant, the right mix of technical and crafty. I'm not sure I'm capable of actually doing it though - I struggle with most hardware stuff.
I taught a TT course at the local Makerspace last year, I'm pretty convinced that most capable programmers can be taught some simple verilog and can knock out a simple design pretty easily
The hard part is learning to think about time and heavy microparallelism so start with something simple
The basic idea is that you buy a chunk of a die, your design's pins get multiplexed to the outside, you pay a bit extra and get a dev board
Chips take time - I taped out my 2 TinyTapeout CPU designs over a year ago, the board arrived a couple of months ago, TT3 is (as I understand) almost in the mail (I have a PDP8 there), and TT4 silicon has just come back (I have a RISCV subset there), TT5 is at the fab, and TT6 tapes out in 2 weeks.
Real silicon works like this, you start on a (big) design, do the creative stuff for a couple of months, for a year you test it to hell, by the time you tapeout you're done with it, then you start on the next design, about the time you're in the middle if doing the fun creative bit the old silicon comes back