Your explanation is great except for the beginning of the story: in the 80s and early 90s, CISC cores didn't have a CISC to RISC decoder frontend - they implemented complex instructions directly (though with the help of microcode). The size penalty of that was more like 300%, and it was slower, too(!). RISC was a really big deal at the time. It was even mentioned in the, ahem, documentary "Hackers" from 1995.
A "CISC to RISC decoder" isn't properly a decoder, it's a translator. What they had in the 80's were proper decoders: instruction's in, enable and clock lines out.
I don't want to argue about that. My point is just that the size (transistor count) and performance differences were massive at the time, like 2-3x the performance at 1/4th or so of the size.
