Hadn't heard of diamond CMOS technology before so did some brief digging. Here's[2] the preprint of the article they refer to for the P-type diamond FET. It uses boron nitride as the insulating layer and graphite for the gate.
I also found this[3] paper discussing a P-type diamond FET using aluminium oxide as the insulating layer, which is also used for the N-type diamond FET.
Some excerpts from the full article:
For high-frequency operation, compared with H-terminated transistors with a cutoff frequency of over GHz, the series resistance is still large for n-type diamond MOSFETs, which is over 10^9 Ω mm^−1 at room temperature. Thus, the operating speed was limited to the kilohertz range.
By optimizing the device geometries, such as the reduction of the drift region space and gate length, the operation frequency can exceed the megahertz range [...]
So seems it's still some significant hurdles to overcome to make it widely useful, but should be good enough for certain niche applications already.
Somewhat related, yesterday there was a post about a new 6.2 GHz Intel CPU and I was wondering how fast the transistors in current CPUs are. The latest number I read - I think 2008ish - is that there are about 25 gate delays per pipeline stage which would give an upper limit of about 6.5 ps. Does anyone publish that kind of numbers for state-of-the-art processes?
They have tested their devices at 300 Celsius degrees, but significantly higher temperatures should be possible, e.g. 500 or 600 Celsius degrees.
It is likely that the upper working temperature would not be limited by the semiconductor channel, but by the accelerated degradation of the metallic conductors, which would limit the lifetime of the devices. Conductors with better chemical and electromigration resistance would have higher electric resistivity, lowering the speed of the devices.
Good question. Couldn't see any immediate answer. They characterize the device at 300C, but the supplemental material[1] shows experimental data on the phosphorus layer up to 600C.
Hadn't heard of diamond CMOS technology before so did some brief digging. Here's[2] the preprint of the article they refer to for the P-type diamond FET. It uses boron nitride as the insulating layer and graphite for the gate.
I also found this[3] paper discussing a P-type diamond FET using aluminium oxide as the insulating layer, which is also used for the N-type diamond FET.
Some excerpts from the full article:
For high-frequency operation, compared with H-terminated transistors with a cutoff frequency of over GHz, the series resistance is still large for n-type diamond MOSFETs, which is over 10^9 Ω mm^−1 at room temperature. Thus, the operating speed was limited to the kilohertz range.
By optimizing the device geometries, such as the reduction of the drift region space and gate length, the operation frequency can exceed the megahertz range [...]
So seems it's still some significant hurdles to overcome to make it widely useful, but should be good enough for certain niche applications already.
[1]: https://onlinelibrary.wiley.com/doi/full/10.1002/advs.202306...
[2]: https://arxiv.org/abs/2102.05982
[3]: https://www.tandfonline.com/doi/full/10.1080/26941112.2022.2...