Dynamic switching power consumption is proportional to frequency which is why things slowed down dramatically once we hit 1Ghz.
Of course you must reduce voltages to reduce current and losses... but at a certain point your transistors no longer switch between clear on/off states because the voltage swing is too small. This is a quantum effect of all semiconductors (related to their valence band energy IIRC). The tiny leakage this represents only makes your heat dissipation story much worse. So you end up trapped between two walls: higher voltage is required to drive the transistor between full on-off states but lower voltage is required to keep the gate from burning itself up. No matter what material you pick (silicon, germanium, etc) there is some minimum voltage required.
Also your insulating layers become a problem as they shrink: quantum tunneling allows electrons to jump the insulating layer. There's a tradeoff here too... alternative oxide layers reduce leakage at the gate but have worse barrier constants and so are prone to more quantum tunneling (related to conduction band energy).
Adding more layers just makes more problems, as each layer you stack risks mangling the layer below it. Plus the risk of introducing a defect. The more defects you have the worse your yields and the more expensive the chip gets.
The short version is: we are at the point where no matter which direction we go some quantum effect kicks in to cheat us out of further optimizations in that direction.
Dynamic switching power consumption is proportional to frequency which is why things slowed down dramatically once we hit 1Ghz.
Of course you must reduce voltages to reduce current and losses... but at a certain point your transistors no longer switch between clear on/off states because the voltage swing is too small. This is a quantum effect of all semiconductors (related to their valence band energy IIRC). The tiny leakage this represents only makes your heat dissipation story much worse. So you end up trapped between two walls: higher voltage is required to drive the transistor between full on-off states but lower voltage is required to keep the gate from burning itself up. No matter what material you pick (silicon, germanium, etc) there is some minimum voltage required.
Also your insulating layers become a problem as they shrink: quantum tunneling allows electrons to jump the insulating layer. There's a tradeoff here too... alternative oxide layers reduce leakage at the gate but have worse barrier constants and so are prone to more quantum tunneling (related to conduction band energy).
Adding more layers just makes more problems, as each layer you stack risks mangling the layer below it. Plus the risk of introducing a defect. The more defects you have the worse your yields and the more expensive the chip gets.
The short version is: we are at the point where no matter which direction we go some quantum effect kicks in to cheat us out of further optimizations in that direction.