> Intrinsic vmulq_f32(x, c0, 0) multiplies each lane of register x with lane 0 from register c0.
I don't remember seeing anything like that NEON instruction in AltiVec or SSE so it didn't even occur to me to look for it when I ported some SIMD code to NEON; now I'm going to go back and look for opportunities to use it!
That should be vmulq_lane_f32(), but yeah, lane broadcast is free on a number of NEON operations. Many operations also have built-in narrowing, widening, saturation, and rounding. One of the more ridiculous ones is vqrdmlah_lane_s16(), which translates to: signed saturating rounding doubling multiply accumulate returning high half (with a lane broadcast).
The downside is that the latencies can be a bit high sometimes compared to other CPUs. 128-bit vector integer adds, for instance, have 2c latency even on an Apple M1.
Another thing to watch out for is that some NEON guides are outdated and only tell you about ARMv7 features, missing some goodies added in ARMv8 like horizontal operations (vaddv) and rounding on conversions other than truncate.
On Intel/AMD you need AVX-512 support to get the instructions with broadcast (and many other goodies that are missing from SSE/AVX/AVX2).
Intel had such instructions many years before ARM (i.e. since Larrabee), but they have chosen to provide them only in their high-end CPUs, annoying the programmers that would like high performance but who do not like the burden of developing for a fragmented instruction set.
> Intrinsic vmulq_f32(x, c0, 0) multiplies each lane of register x with lane 0 from register c0.
I don't remember seeing anything like that NEON instruction in AltiVec or SSE so it didn't even occur to me to look for it when I ported some SIMD code to NEON; now I'm going to go back and look for opportunities to use it!