I've never done it myself, but isn't the stacking connector just as easy as grabbing DF40HC(3.0)-100DS-0.4v (https://www.digikey.com/en/products/detail/hirose-electric-c...), throwing it into a KiCAD 2-layer or 4-layer board (depending on how complex you want to make it), and then just... that's it?
There's no RAM or other complex signals at play here. I have to imagine that 2-layer boards are sufficient for the vast majority of CM4 board users.
I guess a few elements in the connector (USB and Ethernet) are differential pairs. So okay, you need to know a bit about transmission line theory. But as far as actually running differential pairs with matched-impedances, its just a matter of knowing what a "dielectric constant" is and plugging that into the calculator, so that you know how thick the PCB-trace should be in a stripline.
Which is all nearly automatic even with free tools like KiCAD today. Okay, you need to know what the word "dielectric constant" is and that striplines are an impedance-controlled design pattern wherein the width of the PCB-trace on top is matched to a ground-plane below... and that you need the words "Dielectric Constant" and and "Board Thickness" to calculate the width for the impedance you're looking for.
But bam, now you know everything for simpler signals like USB or Ethernet. But honestly, whatever PCB you're designing is probably so small that it'd still work without needing to know any of this deeper theory.
> I guess a few elements in the connector (USB and Ethernet) are differential pairs. So okay, you need to know a bit about transmission line theory. But as far as actually running differential pairs with matched-impedances, its just a matter of knowing what a "dielectric constant" is and plugging that into the calculator, so that you know how thick the PCB-trace should be in a stripline.
You understand that none of this is doable by anyone without a background in EE, don't you?
Bam. Now 9.814 mil thickness for differential pair Ethernet routes.
Yeah, it will take you some study. But I literally laid everything out in front of you with my post above. It shouldn't take you any more than like 30 minutes of studying at this point now that I put everything in just a few posts for you.
An EE Degree will help. But... there's not much to this particular issue. You need to understand that different manufacturers have different thicknesses, dielectric-constants and other such measurements. But its all plug-and-play once you know how to read a spec-sheet.
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If that's too hard, just don't route Ethernet or USB I guess? There aren't very many differential-pair lines or impedance-matched lines on the Rasp. Pi4 CM as far as I can tell.
For large values of 'just', yes. I've been doing electronics for > 40 years and when I say it is beyond my ability then that's just that. I've built (large) RF transmitters and various other HF stuff but this connector spells 'don't even try it' to me.
The most critical portion of the connector is MicroSD, which is just simple SPI signaling. (This is how the Rasp. Pi CM4 seems to boot up from).
There's "difficult" portions: PCIe 2.0, HDMI, Ethernet, and USB 2.0 are all differential pairs. But all of them seem optional and can be left disconnected. I don't expect the differential pair to be especially hard to do in KiCAD if you need one of these features though.
Looking through the manual, I can see that Rasp. Pi CM4 requires 3x power rails (5V, 3.3V, and 1.8V), as well as a startup sequence wherein enable-pins come up at the right timing. But a few MOSFETs and a few capacitors in the right places solve that problem (and maybe a couple hours of simulation in LTSpice).
In my experience though, popular parts will have power-up sequences figured out somewhere. There's probably a chip that just automatically starts up a Rasp. Pi CM4 by now (and if not, at least a premade design that we can copy/paste from the internet).
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What looks difficult to you about the Rasp. Pi CM4??
I've put together some small scale SMD stuff. My hands are no longer steady enough to be able to do this stuff reliably, a USB connector is about the limit of what I can manage (under a microscope, at that) manually so that rules out simply connecting to the module directly.
So any kind of use of this device starts off with PCB design whereas the most obvious uses for me would be to use them to create computing fabrics so I'd like to be able to just send power and networking to them but then I'm suddenly back at the regular raspberry pi. I don't see the point of having 400 lines into and out of a compute node. I'd simply like a denser version of the Pi that still has enough RAM to make it count.
The Pico with castellated i/o is about my comfort zone, but it is hard to use that for any kind of networked solution (or you'd have to go wireless).
Of course you could use a breakout board and just wire up power and ethernet but then you're already back to the same price of a regular Pi and you lose the density advantage.
Fair enough. 0.4mm pitch is definitely looking difficult from a physical assembly perspective.
I guess I thought you were talking about the difficulty of the PCB design, not necessarily the physical tweezers + soldering iron needed to assemble this.
Between failing eyesight (+3.5 now) and unsteady hands this stuff is way out of my league right now and I don't think I have to hope for a reversal on either. Maybe I could train one of my kids ;) Of course I could design a board and order that but that sort of negates the whole advantage. I liked the SODIMM edge connector format much better (and at 0.6 mm pitch it too is probably outside of my comfort zone, but not nearly as far and with some tricks I can probably do that).
The real reason I think I'm a bit disappointed is that Raspberry Pi stuff tends to the end of the hobbyist market where a low barrier to entry is what gets people into the devices and this one breaks that pattern it is simply an industrial intermediary product, not something aimed at end users.
10 years ago, students needed to spend like $300 to $600 of their own money each time they designed something like I described above.
Today, it's like $30 a try.
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Yes, I'm pretty confident that anyone will get it within... 20 tries or so. Or do you think that students 10 years ago got it right on their first try as well?
Like seriously: if you screw up just try try again. It's so much cheaper to get PCBs done today that it's ridiculous. And KiCAD is now a good free solution with calculators and all sorts of crap that Eagle never gave us.
I wish I learned in this easy and cheap environment y'all kids are in today.
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As long as you aren't like, selling this stuff to the public but are instead just doing hobby level tinkering.... You are probably fine.
On a side note, when did this term "compute" work its way into the lexicon? "Compute nodes", etc. I don't recall this being a term until the last year or so.
Most supercomputer clusters are divided into compute-nodes vs management nodes. I'd have to imagine the language was popular as far back as the 1980s in the high-performance computing realm...
Supercomputers were not clusters like we have today until the mid-90's.
In the first written description of how to build a Beowulf cluster, by Radajewski and Eadline in 1998 [1], the management node was refered to as the "server node" and the compute nodes as "client nodes".
I believe the term "compute node" was first used in the context of the Intel ASCI Red supercomputer that was installed at Sandia in 1997. This later led to the Cray XT3, XT4, XT5 families of machines that used the same terminology.
But I believe the term was not in generic usage outside of those specific supercomputers until around 2005-2010.
I've seen this a lot in contexts with specific workloads the last 10 years or so. With both physical space and PCIE lanes being factors, as well as how you handle virtualization/barebones setups. This can help with simplifying failover as well for HA.
For example, storage servers usually are full to the brim of harddrives and SSDs.
Then you might need to process your data on GPUs/CPUs where you have specific servers specced out with more CPU/GPU resources.
