I am hopeful we'll have a "miSTress" or some similar such name as followup to miST/miSTer.
To adopt a cheaper, more modern, and more powerful FPGA ecosystem that's actually supported by the yosys/nextpnr open stack. And, while at it, the control plane CPU would be standard RISC-V instead of legacy ISA (currently ARM).
Something like Lattice ECP5 or GOWIN's GW2N.
On that, Sipeed recently announced a cheap 135K LUT devboard[0] based on GW2N. Apparently, a version with ~500k LUT is in the works.
Two Cortex-A9s are better than soft cores, for sure, but pretty far from four 64 bit U54 applications processors plus a 64 bit S51 [1] real-time core if you want to do any serious CPU-based processing.
[1] called E51 when this U54-MC core complex first came out in the FU-540 SoC on the HiFive Unleashed in 2018. That was running at 1.0 - 1.5 GHz vs 667 MHz in this FPGA, but otherwise the same thing.
$30 is a good price for FPGA dev board, requires a little creativity https://github.com/q3k/chubby75/tree/master