And if they build 3D cache capability into the Bergamo CCD, that would still blow up the die size (from the TSVs) and not alleviate some workloads anyway.
For the Zen 3 generation, AMD quietly mentioned that they skipped the 5950X3D because there was too much congestion between the CCDs, thanks to all the extra L3 they were trying to access. The IF links got saturated.
Maybe something similar would happen to Bergamo as well. Even if there's enough memory bandwidth, the IO die just gets saturated with all the CCD slots active.
For the Zen 3 generation, AMD quietly mentioned that they skipped the 5950X3D because there was too much congestion between the CCDs, thanks to all the extra L3 they were trying to access. The IF links got saturated.
Maybe something similar would happen to Bergamo as well. Even if there's enough memory bandwidth, the IO die just gets saturated with all the CCD slots active.