> There's also a FPGA implementation of the 6502 CPU running at 100Mhz, that's on a Spartan 6
There are plenty of free RISC-V soft cores that will run at 100 MHz on an FPGA, and that's at 1 instruction per cycle, not the 2-6 cycles per instruction that 6502 takes. Also a 32 or 64 bit RISC instruction does a lot more useful work than a 6502 instruction e.g. `add Rd, Rs1, Rs2` is one instruction and one clock cycle vs 13 instructions and 38 clock cycles for a 6502 to add two 32 bit numbers at fixed locations in Zero Page (virtual registers, if you like).
There are plenty of free RISC-V soft cores that will run at 100 MHz on an FPGA, and that's at 1 instruction per cycle, not the 2-6 cycles per instruction that 6502 takes. Also a 32 or 64 bit RISC instruction does a lot more useful work than a 6502 instruction e.g. `add Rd, Rs1, Rs2` is one instruction and one clock cycle vs 13 instructions and 38 clock cycles for a 6502 to add two 32 bit numbers at fixed locations in Zero Page (virtual registers, if you like).