I haven't tested a physical chip to verify, but based on my simulations I think you are correct. For your second example, a side effect is that NMI is blocked until the end of the instruction, so you could block the NMI interrupt for an arbitrary amount of time.
Oh wow. NMI blocked, and presumably other interrupts too? That means the filling a 64K segment with cs: prefixes will lock the CPU completely. IP will wrap around forever, and you have created some kind of infinite sized instruction. That's kind of cool!
Presumably, yeah. If other interrupts weren't blocked, unless PC is somehow saved to be the address of the prefix(es), upon exiting from the interrupt you'd resume from the "wrong" ("incomplete", lacking its prefix) instruction.
Question: Does the 1BL thing imply that the 8086 is not capable of detecting useless prefixes? So the next 2 implications are correct:
Eg1: lock cs: clc is just treated as clc, and the lock and cs: are ignored?
Eg2: The 8086 has no 16 byte instruction length limit, unlike some successors. So e.g 16 seg overrides:
Cs: Ds: Es: Ss: Cs: Ds: Es: Ss: Cs: Ds: Es: Ss: Cs: Ds: Es: Ss: mov [1234],5
Is just ss: mov [1234],5