Nah, it was just poorly designed. Intel promised two things for IA64: more instructions per clock and much higher clock rates. The first promise failed to materialize due to suitable compilers being much too difficult to implement, which in turn stopped investments in silicon improvements (which, in hindsight, would have been extremely challenging as well).
- the promised compilers are _impossible_ as we can't predict all branches and all cache misses in _general_ (works better for floating point heavy code),
- the failure to clock higher was IMO largely due to a ridiculously bloated and over-complicated ISA. In other words, EPIC was doomed from birth.
I've written about IA-64 many times; it actually had many neat ideas, but in the end Intel yet again failed spectacularly in moving away from their archaic legacy.
> the failure to clock higher was IMO largely due to a ridiculously bloated and over-complicated ISA.
Perhaps mostly due to having too many architected registers AND making most of them rotating/part of register windows... that means more work to do per instruction. Wide superscalar => you need lots and lots of forwarding paths between the ALUs. Combined with no out of order execution to allow for spreading that work out a bit (longer latencies per instruction but largely hidden by other work) and you get hard limits on the clock speed.
