On: TinyEMU – x86 and RISC-V emulator, small and simple while being complete

[moloch-hai]

The B extension never gets any love.

The RISC-V crowd hates bitwise anything.

[snvzz → moloch-hai]

B extension was ratified in 2021, near the end.

It is considerably newer than every extension this emulator implements, and thus reasonable it'd have these and not B.

[mncharity → snvzz]

Here's the ratified spec[1]. And some class slides[2]. And a list of other recent extensions[3].

[1] https://github.com/riscv/riscv-bitmanip/releases/download/1.... from https://github.com/riscv/riscv-bitmanip/releases . [2] https://courses.cs.washington.edu/courses/cse481a/20sp/notes... [3] https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...

[gary_0 → snvzz]

Hopefully B becomes ubiquitous in the next generation of SoC's, or RISC-V is going to look bad in any benchmarks that happen to have a popcnt in the hot path.

[nullc → gary_0]

I worry a bit that B is too ambitious with many instructions that no one is using yet which are difficult to prove their value as a result, while regular RISC-V is essentially hobbled compared to ordinary cpus due to the absence of popcnt/clz.

[snvzz → nullc]

Most implementations announced recently (e.g. in RISC-V Summit last December) have B.

Even the newer revisions of cores that have been available for a while (like SiFive U74) have been updated with B support.

As such, I believe it to be a non-issue. Hardware simply takes time.

>which are difficult to prove their value as a result,

As with any RISC-V extensions, each instruction had to meet many criteria to be allowed in there.

Rationale accompany the instructions in the documentation.

[nullc → snvzz]

> Most implementations announced recently (e.g. in RISC-V Summit last December) have B.

That's fantastic.

> Rationale accompany the instructions in the documentation.

I've read it-- I didn't personally need it to be convinced, but I'm surprised it convinced vendors. Glad to hear that it has.

[snvzz → gary_0]

At least Zba, Zbb and Zbs are in RVA22 iirc.

edit: Zbs.

[gary_0 → snvzz]

Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)

[moloch-hai → snvzz]

Zbc (carryless multiply) seems to be needed to implement AES-GCM

[snvzz → moloch-hai]

It is required in Zkn (Scalar Crypto NIST Algorithms) and Zks (Scalar Crypto ShangMi Algorithms).

[snvzz → gary_0]

>Hopefully B becomes ubiquitous in the next generation of SoC's

Hopefully together with V.

[cbm-vic-20 → snvzz]

B instructions are also recognized by the GNU bunutils assembler.