On: MIPS provides highly scalable RISC processor IP

[yjftsjthsd-h]

I know this is a kind of stupid little thing, but I really wish they'd rebranded more completely if they were going to do this. "That box has a MIPS processor in it. But not a MIPS processor, a MIPS RISC-V processor." We're going to end up with OSs list on their "supported platforms" page things like MIPS, MIPS64, MIPS-brand RISC-V.

[dkersten → yjftsjthsd-h]

Its not really a "stupid little thing", it sounds like a big cause of confusion.

[jogu → yjftsjthsd-h]

To be fair this isn't an announcement of a product or anything like that, so their line of RISC-V processors could have distinct branding e.g. FooBar RISC-V Processors (by MIPS).

Totally agree though that they should probably be careful and put some thought into how they brand these.

[gpderetta → yjftsjthsd-h]

RISC-V itself is a very confusing branding. "Not a MIPS RISC processor, a MIPS RISC-V processor!"

[HideousKojima → yjftsjthsd-h]

ARM has been doing basically the same thing for decades now with all the different sub versions of ARMv7, 8, 9 etc.

[yjftsjthsd-h → HideousKojima]

Those are versions of the same(ish) ISA and are (usually?) backwards compatible. I'd mind less if MIPS-the-company made CPUs that were RISC-V with a MIPS-the-ISA compatibility mode, or otherwise actually had continuity; it's the apparent plan to throw away the ISA but keep the name that's jarring.

[dragontamer → yjftsjthsd-h]

ARM Cortex M0+ looks nothing like ARM v8.

ARM Cortex M0+ has more similarities with the ATTiny84 / Arduino chips than with cellphone-sized ARMs.

[pajko → dragontamer]

Cortex M0+ is ARMv6-M. ARMv8 has also an M variant, Cortex M33 is ARMv8-M mainline. ARMv6-M and ARMv8-M have quite a lot of things in common, as v8 is a superset of v6. Or did you mean ARMv8-A? Well, ARMv8-A and ARMv8-M are not compatible intentionally, as the the A variant is strictly 64-bit (some implementations support AArch32 though) and the support for thumb instruction set has been dropped.

[GoblinSlayer → yjftsjthsd-h]

That's reasonable: RISC-V is mostly a cleaned up MIPS, so can definitely go as a MIPS family ISA.

[pajko → GoblinSlayer]

MIPS is as cleaned up as needs to be. RISC-V removed important features and adds loads of bloats via extensions.