This line is nonsense and you can safely ignore it. There have been multi-chip-modules that act like a single socket for many years. In particular, pretty much every current AMD CPU works that way. I guarantee you that for the M1 Ultra, just like every CPU before it, the abstraction will be leaky. Programmers will still care about the interconnect when eking out the last few percent of performance.
Remember the Pentium D? Unfortunately, I used to own one.
The existing AMD CPUs aren't quite like that. Technically they are all UMA, not NUMA - the L3 cache is distributed, but they are all behind a single memory controller with consistent latencies to all cores. But the Threadripper 1st gen was absolutely like that. Straight up 2+ CPUs connected via infinity fabric pretending to be a single CPU. So is that 56 core Xeon that Intel was bragging about for a while there until the 64 core Epycs & Threadrippers embarrassed the hell out of it.
>Technically they are all UMA, not NUMA - the L3 cache is distributed, but they are all behind a single memory controller with consistent latencies to all cores.
This stuff rapidly starts to make my head spin. I have not studied interconnects and have never written any NUMA-aware software. I will just post this link (read the "Memory Latency" section):
As I understand it, the I/O die is partitioned into four quadrants. Each quadrant has two memory controllers and is attached to two compute dies. CPUs can access memory attached to the same quadrant with lower latency than going to another quadrant. This is a NUMA system that can be configured to appear as one logical NUMA node.
I believe their smaller parts with two or fewer compute dies will be UMA, but with the same non-uniform latency to L3.
>So is that 56 core Xeon that Intel was bragging about for a while there until the 64 core Epycs & Threadrippers embarrassed the hell out of it.
I believe the 64-core Epycs and Threadrippers came first. The 56-core Xeon was a purpose-built part for HPC, so it wasn't quite a marketing gimmick.
Remember the Pentium D? Unfortunately, I used to own one.