> but I really don't think it would have been much of a stretch to design the instruction set with traps in the right place to allow software to implement infinite nestability
Nested virtualisation is available for server cores starting from Neoverse V1 onwards, but not for Cortex…
(Also, EL0 could be used as a problem state for this, but some complexities associated to that make it awkward. Unlike POWER (which does have KVM-PR), VBAR doesn’t link to a physical address)
Nested virtualisation is available for server cores starting from Neoverse V1 onwards, but not for Cortex…
(Also, EL0 could be used as a problem state for this, but some complexities associated to that make it awkward. Unlike POWER (which does have KVM-PR), VBAR doesn’t link to a physical address)