I'm not guessing. They are different dies. There is no need to write a hypothetical wall of text and get it wrong; you can just look up die shots or chip package shots or device trees and know they're different dies. This information is well known. There's a massive difference in size and aspect ratio between all 3 dies. It would not be cost efficient to fab M1 Max dies and sell them as M1 Pro. The M1 Max is explicitly designed as a logical and layout superset of the M1 Pro, but not for binning purposes, just because that way they don't need to do two completely different layouts.
The Pro isn't a flat out cropped Max; you can tell because the bottom edge looks like a proper die edge, and there are subtle places where the break line wouldn't be straight (compare the DDR channels with the rest of the blocks, they don't line up slightly). The Max is a cropped real Max because they tried to hide the die-to-die interconnect (meant for a 2-die Max machine) at the bottom. You can tell because the die abruptly stops at that edge hard, without the expected features of an IC edge. Clearly if they'd gone as far as photoshopping that on for the Pro, they wouldn't have screwed it up on the Max ;-)
I'm not aware of any other public die shots of the Pro, but there is one of the Max that went around on Twitter and it matches the marketing shot, plus an extra strip on the bottom edge as we'd suspected. We do know the M1 Pro has a completely different and smaller package, however, and the M1 Max die would not fit on it. That one was leaked months before the announcement as part of the board layout and schematics for that machine. So the Max die simply wouldn't fit on Pro machines, and this is from engineering drawings.
If the metal isn’t there it won’t show up in device tree because it physically isn’t connected on the die. So device tree as you keep pointing out cannot tell you if it’s same die or not. Also the device can be there and not be in device tree meaning the devices memory location was omitted from device tree when the device tree blob was built.
It may well be that they have different die. But that’s usually an expensive way to do things. Usually you want downgrade paths for devices that don’t yield.
They do have downgrade paths for chips that don't yield: disabling some CPU or GPU cores, but not half the chip. That's why Apple sells those variants. Also, the M1 Max die physically doesn't fit on the substrate used for the M1 Pro.
Source: over one year working on reverse engineering this precise platform almost full time.
Also, if you've spent 23 years in the semiconductor industry, I have no idea where you're getting the "not connecting metal" story. Nobody does that. How would you even do that for a yield issue? That doesn't make any sense. Chips that have failed bits get the broken parts marked bad via eFuses after production and the initialization logic or bootloader will then read the fuses and power/clock gate those bits and lock them in that state, via existing isolation/gate logic. That's how the entire industry does it. Metal patches are for fixing design bugs in a respin and stuff like that, not for turning things off in a finished chip. And you certainly wouldn't make a change in the line to the metal to disable half a chip from the get go. That's just throwing silicon away for no reason, why wouldn't you try building the full thing first and seeing what works? The entire concept makes no sense.
SoC codes T8103 (M1), T6000 (M1 Pro), T6001 (M1 Max).
Yes, they do use binning and e-fuses for the lower core count versions within each die/SoC type.