On: Verilog Simulation with Verilator and SDL

[beefok]

I come from a VHDL background (the industry I work in is purely VHDL), but recently I've been enjoying Systemverilog in my personal projects and it fixes a lot of these issues!

You can even do:

  typedef enum bit[1:0] {

    my_one, my_two, my_three, my_four

  } my_enum;

  typedef struct packed {

    my_enum b,

    bit [3:0] x

  } my_struct

  my_struct.b <= my_three;

etc...

It's been a nice path since I last dealt with Verilog. The concept of interfaces makes struct/vector input/output even nicer.

[UncleOxidant → beefok]

It's true that SystemVerilog fixed a lot of Verilog's deficiencies and took it more in the direction of VHDL. But a lot of free tools don't support SystemVerilog.

[beefok → UncleOxidant]

Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to?

Thanks!

[mhh__ → beefok]

There isn't much support if any in open source tools, if free means free software.

[gchadwick → mhh__]

There's few open source tools for any HDL full stop.

Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).

[beefok → mhh__]

I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog.

What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.