On: Verilog Simulation with Verilator and SDL

[artisanspam]

While Verilog is not SystemVerilog, it’s more or less a subset of it. And SystemVerilog had much more industry support for design verification. So if I were to design some open source software for HDLs, that reason alone would make VHDL a non-starter.

[teleforce → artisanspam]

Verilog is now officially the subset of SystemVerilog since 2009 [1]. The same can be said now for C since it's supported in both C++ and D compiler.

[1] https://standards.ieee.org/project/1800.html

[NextHendrix → artisanspam]

SystemVerilog and UVM are perfectly capable of being used to verify VHDL designs.

I should also add that if you wanted to use a single language for everything OSVVM is excellent.

[artisanspam → NextHendrix]

Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).