Just like Nios II, it's a processor. It doesn't have to be "hard" silicon. Calling it a "little FPGA program" seems very dismissive. I don't know what you mean by "1990 style".
They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.
> Calling it a "little FPGA program" seems very dismissive.
Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.
> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.
That's inefficient for an FPGA softcore; wires are too expensive, CAMs are straight up awful, and memory latencies aren't too far off relative to the core clock frequencies to justify OOO stuff in the normal case.
> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
Writing a 5 stage is easy.
Writing a 5 stage with no bugs is much harder.
Writing a 5 stage that talks industry standard busses and provides Debug/JTAG Support at high frequency and small gate counts is, well, an actual job.
Not saying you can't do better, but it's not a trivial effort.
> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.
There's a lot of processors out there. The vast, vast majority being shipped are in order and a handful of stages.
> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
> I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.
The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core. They have enough customers for the designs to have enough reach to have the same financial implications for bugs.
The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core.
I'm not sure what you mean by engineering rigor, but there is indeed plenty of engineering to get from a soft core to a hard core, let alone a fabricated, working chip: synthesis, layout, place and route, timing closure, pads, PLL/DLL, clock tree insertion, BIST, thermal, packaging, etc...
High end soft cores do most of that. Particularly when you consider that most of what isn't automated these days is equally applicable to soft cores that aren't just Verilog or VHDl. Floor planning FPGA cores these days can be nutty compared to the recent past (far past interestingly enough was similar before you had higher level tools). And the fact that stuff like packaging, DLLs/PLLs are equally applicable to hard cores. That's outside of what they care about on nearly every core design I've seen (albeit I'm only in my mid 30s).
Intel has a terrible track record with maker-ish stuff. They routinely launch products, sell them for a year, then discontinue them. (Intel Euclid vision SBC, Intel Edison x86 microcontroller, the realsense stuff, etc)
You can't build an ecosystem around a product if you kill it after a few months. Arudino is only Arduino because they actually stuck around.
Well, lately anyway. The 386EX [1] was supported from 1994 to 2006 with many interesting and "cheap" third party SBCs, replaced in 2007 by the Tolpai SOC line which was killed the following year. It's been all churn since then it seems.
You can still buy tons of 386EX chips and boards on eBay and even a couple first-hand (JK Flashlight) and there's a few modern homebrew designs out there.
I think that level of sophistication is typical of soft cores. If you need a high performance CPU you don’t use a soft core. You use a soft core when part of your FPGA project can be more easily expressed as a CPU, but still needs tight coupling with the rest of the FPGA.
This is meant to compete with Cortex-M1 and MicroBlaze, not with Cortex-A78 or Core i9 or something.
You don't have that fancy stuff in really low cost, embedded systems, or as part of the control path in a large, complex FPGA or ASIC design. Look at ARM Cortex M0+, M3, M4 or numerous RISC-V cores for microcontroller applications.
You get the core you need that meets the processing budget with as little cost, area/resources needed and with as little power consumption. That was true then and it is just as true today.
